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PSD813F1AV-12MIT Datasheet(PDF) 82 Page - STMicroelectronics |
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PSD813F1AV-12MIT Datasheet(HTML) 82 Page - STMicroelectronics |
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82 / 110 page ![]() PSD813F1V 82/110 Table 48. CPLD Combinatorial Timing (3V devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. ZPSD versions only. Figure 43. Synchronous Clock Mode Timing – PLD Symbol Parameter Conditions -15 -20 PT Aloc Turbo Off2 Slew rate1 Unit Min Max Min Max tPD CPLD Input Pin/Feedback to CPLD Combinatorial Output 48 55 + 4 + 20 – 6 ns tEA CPLD Input to CPLD Output Enable 43 50 + 20 – 6 ns tER CPLD Input to CPLD Output Disable 43 50 + 20 – 6 ns tARP CPLD Register Clear or Preset Delay 48 55 + 20 – 6 ns tARPW CPLD Register Clear or Preset Pulse Width 30 35 + 20 ns tARD CPLD Array Delay Any macrocell 29 33 + 4 ns tCH tCL tCO tH tS CLKIN INPUT REGISTERED OUTPUT AI02860 |
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