PSD813F1AV-12MIT datasheet(36/110 Pages) STMICROELECTRONICS

36 / 110 page

PSD813F1V

36/110

DECODE PLD (DPLD)

The DPLD, shown in Figure 16, is used for decod-

ing the address for internal and external compo-

nents. The DPLD can be used to generate the

following decode signals:

■

8 sector selects for the main Flash memory

(three product terms each)

■

4 sector selects for the EEPROM (three

product terms each)

■

1 internal SRAM select signal (two product

terms)

■

1 internal CSIOP (PSD configuration register)

select signal

■

1 JTAG select signal (enables JTAG on Port

■

2 internal peripheral select signals (peripheral

I/O mode).

Figure 16. DPLD Logic Array

Note: 1. The address inputs are A19-A4 in 80C51XA mode.

(INPUTS)

(24)

(8)

(16)

(1)

PDN (APD OUTPUT)

I /O PORTS (PORT A,B,C)

(8)

PGR0 - PGR7

(8)

MCELLAB.FB [7:0] (FEEDBACKS)

MCELLBC.FB [7:0] (FEEDBACKS)

A[15:0]

(1)

(3)

PD[2:0] (ALE,CLKIN,CSI)

CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)

(1)

RESET

RD_BSY

RS0

CSIOP

PSEL0

PSEL1

8 FLASH MEMORY

SECTOR SELECTS

SRAM SELECT

I/O DECODER

SELECT

PERIPHERAL I/O

MODE SELECT

EES 0

EES 1

EES 2

EES 3

FS0

FS7

JTAGSEL

AI09226

FS1

FS2

FS3

FS6

FS5

FS4

EEPROM

SELECTS

PSD813F1AV-12MIT Datasheet(PDF) 36 Page - STMicroelectronics

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