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PSD813F1AV-12MIT Datasheet(PDF) 85 Page - STMicroelectronics |
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PSD813F1AV-12MIT Datasheet(HTML) 85 Page - STMicroelectronics |
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85 / 110 page ![]() 85/110 PSD813F1V Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices) Note: 1. ZPSD versions only. Symbol Parameter Conditions -90 -12 -15 PT Aloc Turbo Off1 Slew Rate Unit Min Max Min Max Min Max fMAXA Maximum Frequency External Feedback 1/(tSA+tCOA) 26.3 2 23.25 20.4 MHz Maximum Frequency Internal Feedback (fCNTA) 1/(tSA+tCOA–10) 35.7 1 30.30 25.64 MHz Maximum Frequency Pipelined Data 1/(tCHA+tCLA) 41.6 7 35.71 33.3 MHz tSA Input Setup Time 8 10 12 + 2 + 10 ns tHA Input Hold Time 12 14 14 ns tCHA Clock Input High Time 12 14 15 + 10 ns tCLA Clock Input Low Time 12 14 15 + 10 ns tCOA Clock to Output Delay 30 33 37 + 10 – 2 ns tARDA CPLD Array Delay Any macrocell 16 18 22 + 2 ns tMINA Minimum Clock Period 1/fCNTA 28 33 39 ns |
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