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M69KB096AA

Table 2. Bus Modes– Asynchronous Mode

Table 3. Bus Modes– Synchronous Burst Mode

Note: 1. When LB and UB are in select mode (Low), DQ15-DQ0 are affected. When only LB is in select mode, DQ7-DQ0 are affected. When

only UB is in the select mode, DQ15-DQ8 are affected.

2. The WAIT polarity is configured through the Bus Configuration Register (BCR10).

3. The device consumes active power in this mode whenever addresses are changed.

4. When the device is in Standby mode, Address inputs and Data inputs/outputs are internally isolated from any external influence.

6. The device remains in Deep Power-Down mode until the RCR register is reconfigured.

7. The Synchronous Burst mode is initialized through the Bus Configuration Register (BCR15).

8. The clock polarity is configured through the Bus Configuration Register (BCR6).

9. The Clock signal, K, must remain stable during Burst Suspend operations.

MODE

POWER

K

L

E

G

W

CR

LB, UB

WAIT

(2)

DQ15-DQ0

(1)

NOTES

Asynchronous

Read

Active >

Standby

LL

LL

H

L

Low Z

Data-Out

3

Asynchronous

Write

Active >

Standby

LL

L

X

L

L

Low Z

Data-In

3

Standby

Standby

L

X

H

X

X

L

X

High Z

High-Z

4,5

Write

Configuration

Register

Active

L

L

L

H

L

H

X

Low Z

High-Z

Deep Power-

Down (DPD)

Deep

Power-

Down

L

X

H

X

X

X

X

High-Z

High-Z

6

MODE

POWER

K

L

E

G

W

CR

LB, UB

WAIT

(2)

DQ15-DQ0

(1)

NOTES

Initial Burst

Read

Active >

Standby

!

L

L

X

H

L

L

Low Z

Data-Out

3, 7, 8

Initial Burst

Write

Active >

Standby

!

L

L

H

L

L

X

Low Z

Data-In

3, 7, 8

Subsequent

Burst

Operation

Active >

Standby

!

H

L

XXX

L

Low Z

Data-In or

Data-Out

3, 7, 8

Burst

Suspend

Active >

Standby

X

L

H

X

L

X

Low Z

High-Z

3, 7

Write

Configuration

Register

Active

!

L

L

H

L

H

X

Low Z

High-Z

7, 8

Deep Power-

Down (DPD)

Deep

Power-

Down

L

X

H

X

X

X

X

High-Z

High-Z

6