M69KB096AA datasheet(4/48 Pages) STMICROELECTRONICS

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M69KB096AA

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SUMMARY DESCRIPTION

The M69KB096AA is a 64 Mbit (67,108,864 bit)

PSRAM, organized as 4,194,304 words by 16 bits.

The memory array is implemented using a one

transistor-per-cell topology, to achieve bigger ar-

ray sizes.

This device is a high-speed CMOS, dynamic ran-

dom-access memory. It provides a high-density

solution for low-power handheld applications.

The M69KB096AA includes the industry standard

Flash memory burst mode that dramatically in-

creases read/write over that of other low-power

SRAM or PSRAMs.

The PSRAM interface supports both asynchro-

nous and burst-mode transfers. Page mode ac-

cesses are also included as a bandwidth-

enhancing extension to the asynchronous read

protocol.

PSRAMs are based on the DRAM technology, but

have a transparent internal self-refresh mecha-

nism that requires no additional support from the

system memory controller, and has no significant

impact on the device read/write performance.

The device has two configuration registers, acces-

sible to the user to define the device operation: the

Bus Configuration Register (BCR) and the Refresh

Configuration Register (RCR). The Bus Configura-

tion Register (BCR) indicates how the device inter-

acts with the system memory bus. Overall, it is

identical to its counterpart in burst-mode Flash

memory devices. The Refresh Configuration Reg-

ister (RCR) is used to control how the memory ar-

ray refresh is performed. At power-up, these

registers are automatically loaded with default set-

tings and can be updated any time during normal

operation.

To minimize the value of the standby current dur-

ing self-refresh operations, the M69KB096AA in-

cludes

three

system-accessible

mechanisms

configured via the Refresh Configuration Register

(RCR):

■

The Temperature Compensated Refresh

(TCR) is used to adjust the refresh rate

according to the operating temperature. The

refresh rate can be decreased at lower

temperatures to minimize current

consumption during standby.

■

The Partial Array Refresh (PAR) performs a

limited refresh of the part of the PSRAM array

that contains essential data.

■

The Deep Power-Down (DPD) mode

completely halts the refresh operation. It is

used when no essential data is being held in

the device.

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A21

Address Inputs

DQ0-DQ15

Data Inputs/Outputs

Chip Enable Input

Configuration Register Enable Input

Output Enable Input

Write Enable Input

Upper Byte Enable Input

Lower Byte Enable Input

Clock Input

Latch Enable Input

WAIT

Wait Output

VCC

Core Supply Voltage

VCCQ

Input/Output Buffers Supply Voltage

VSS

Ground

VSSQ

Input/Output Buffers Ground

AI10584b

A0-A21

DQ0-DQ15

VCC

M69KB096AA

VSS

VCCQ

VSSQ

WAIT

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