ST25R3911B datasheet(13/116 Pages) STMICROELECTRONICS

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An IRQ is sent when the difference between a measured value and the reference value is larger than the

configured threshold value. There are two possible definitions for the reference value:

The ST25R3911B can calculate the reference based on previous measurements (auto-averaging)

The controller determines the reference and stores it in a register

The first register in the series of four is the Amplitude measurement configuration register. The difference to the

reference value that triggers the IRQ, the method of reference value definition and the weight of the last

measurement result in case of auto-averaging are defined in this register. The next register is storing the

reference value in case the reference is defined by the controller. The following two registers are display registers.

The first one stores the auto-averaging reference, and the second one stores the result of the last measurement.

The wake-up mode configuration registers have to be configured before the wake-up mode is entered. Any

modification of the wake-up mode configuration while it is active may result in unpredictable behavior.

Auto-averaging

In case of auto-averaging the reference value is recalculated after every measurement as

NewAverage = OldAverage + (MeasuredValue - OldAverage) / Weight

The calculation is done on 13 bits to have sufficient precision.The auto-averaging process is initialized when the

wake-up mode is entered for the first time after initialization (at power-up or after Set Default command). The

initial value is taken from the measurement display registers (for example Amplitude measurement display

Every Measurement Configuration register contains a bit that defines whether the measurement that causes an

interrupt is taken in account for the average value calculation (for example bit am_aam of the Amplitude

measurement display register).

1.2.6

Quartz crystal oscillator

The quartz crystal oscillator can operate with 13.56 MHz and 27.12 MHz crystals. The operation of quartz crystal

oscillator is enabled when the Operation control register bit en is set to one. An interrupt is sent to inform the

microcontroller when the oscillator frequency is stable (see Section 1.3.24 Main interrupt register).

The status of oscillator can be observed by observing the Auxiliary display register bit osc_ok. This bit is set to ‘1’

when oscillator frequency is stable.

The oscillator is based on an inverter stage supplied by a controlled current source. A feedback loop is controlling

the bias current in order to regulate amplitude on XTI pin to 1 Vpp.

To enable a fast reader start-up an interrupt is sent when the oscillator amplitude exceeds 750 mVpp.

Division by two ensures that 13.56 MHz signal has a duty cycle of 50%, which is better for the transmitter

performance (no PW distortion). Use of 27.12 MHz crystal is therefore recommended for better performance.

In case of 13.56 MHz crystal, the bias current of stage that is digitizing oscillator signal is increased to assure as

low PW distortion as possible.

Note:

In case of VHBR reception (bit rates fc/8 and above) it is mandatory to use the 27.12 MHz crystal since high

frequency clock is needed for receive framing.

The oscillator output is also used to drive a clock signal output pin MCU_CLK) that can be used by the external

microcontroller. The MCU_CLK pin is configured in the IO configuration register 2.

1.2.7

Timers

The ST25R3911B contains several timers that eliminate the need to run counters in the controller, thus reducing

the effort of the controller code implementation and improve portability of code to different controllers.

Every timer has one or more associated configuration registers in which the timeout duration and different

operating modes are defined. These configuration registers have to be set while the corresponding timer is not

running. Any modification of timer configuration while the timer is active may result in unpredictable behaviour.

All timers except the wake-up timer are stopped by direct command clear.

Note:

In case bit nrt_emv in the General purpose and no-response timer control register is set to one, the no-response

timer is not stopped

Mask receive timer and no-response timer

Mask Receive timer and no-response timer are both automatically started at the end of transmission (at the end of

EOF).

ST25R3911B

Application information

DS11793 - Rev 6

page 13/116

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