ST25R3918 datasheet(39/141 Pages) STMICROELECTRONICS

39 / 141 page

DS13490 Rev 2

39/141

ST25R3918

Application information

140

Preparation and execution of a transceive sequence:



Execute the direct command Stop all activities



Execute the direct command Reset RX gain



Configure the timers accordingly



Define the number of transmitted bytes in the Number of transmitted bytes register 1

and Number of transmitted bytes register 2



Write the bytes to be transmitted in the FIFO (not in the case of direct commands

REQA and WUPA)



Send one of the commands Transmit with CRC, Transmit without CRC, Transmit

REQA or Transmit WUPA



When all the data is transmitted an interrupt is sent to inform the microcontroller that

the transmission is finished (IRQ due to end of transmission)

After the transmission is executed, the ST25R3918 receiver automatically starts to observe

the RFI inputs to detect a transponder response. The RSSI and AGC (in case it is enabled)

are started. The framing block processes the subcarrier signal from receiver and fills the

FIFO with data. When the reception is finished and all the data is in the FIFO an interrupt is

sent to the microcontroller (IRQ due to end of receive), and the FIFO status register 1 and

FIFO status register 1 display the number of bytes in the FIFO so the microcontroller can

proceed with data download.

If an error or bit collision is detected during reception, an interrupt with appropriate flag is

sent, and the microcontroller must take appropriate action.

When data packets longer than FIFO have to be transmitted the sequence detailed above

changes.

The FIFO is prepared with data before the transmission starts. An interrupt is sent during the

transmission to signal when the remaining number of bytes is lower than the water level

(IRQ due to FIFO water level). The microcontroller then adds more data in the FIFO. When

all the data are transmitted an interrupt is sent to inform the microcontroller that the

transmission is finished.

The situation during reception time is similar. When the FIFO is loaded with more data than

the receive water level, an interrupt is sent and the microcontroller reads the data from the

FIFO. When the reception is finished an interrupt is sent to the microcontroller (IRQ due to

end of receive) the FIFO status register 1 and FIFO status register 1 display the number of

bytes in the FIFO still to be read.

4.2.12

Listen mode

The ST25R3918 listen/target mode is activated by setting to 1 bit targ in the Mode definition

the om<3:0> bits, refer to Table 20: Target operation modes.

The main modes are



ISO14443A passive target mode



Felica™ passive target mode

Fixed listen communication mode

Fixed communication mode is active when one of the target modes with om3=0 is selected.

The other om bits control the type of communication.

ST25R3918 Datasheet(PDF) 39 Page - STMicroelectronics

ST25R3918 Datasheet(HTML) 39 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL