STM32L010K8 datasheet(26/92 Pages) STMICROELECTRONICS

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Functional overview

STM32L010K8 STM32L010R8

26/92

DS12325 Rev 3

In addition, I2C1 provides hardware support for SMBus 2.0 and PMBus 1.1: ARP capability,

Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and

ALERT protocol management. I2C1 also has a clock domain independent from the CPU

clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.

The I2C interface can be served by the DMA controller.

Refer to Table 6 for the supported modes and features of I2C interface.

3.14.2

Universal synchronous/asynchronous receiver transmitter (USART)

The USART interface (USART2) is able to communicate at speeds of up to 4 Mbit/s.

It provides hardware management of the CTS, RTS and RS485 driver enable (DE) signals,

multiprocessor communication mode and single-wire half-duplex communication mode.

The UART2 interface can be served by the DMA controller.

Table 7 for the supported modes and features of the USART interface.

Table 6. I2C implementation

I2C features(1)

1. X = supported.

I2C1

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast mode plus with 20 mA output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from Stop

Table 7. USART implementation

USART modes/features(1)

USART2

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode(2)

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

Modbus communication

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