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STE2001 Datasheet(PDF) 6 Page - STMicroelectronics

Part # STE2001
Description  65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
PDF  36 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE2001 Datasheet(HTML) 6 Page - STMicroelectronics

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Notes: 1.
2. RES may be LOW or HIGH before VDD1 goes HIGH.
3. If Tw(RES) is longer than 500ns (typical) a reset may be generated.
4. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with
an input voltage swing of VSS to VDD
5. The rise and fall times specified here refer to the driver device and are part of general Hs-mode specification.
6. The device inputs SDA and SCL are filtered and will reject any spike on the bus-lines of with TSW
7. Cb is the capacitive load for each bus line.
8. TH5 is the time from the previous SCLK positive edge to the negative edge of SCE
9. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
10.CVLCD is the filtering capacitor on VLCDOUT
11.If Tw(RES) is shorter than max. value a reset pulse is rejected.
TfDA
Cb=100pF
25
ns
TfDA
Cb=400pF
120
ns
Cb
Capacitive load for SDAH and
SCLH
100
400
pF
Cb
Capacitive load for SDAH + SDA
line and SCLH + SCL line
400
pF
TSW
note 5
10
ns
PARALLEL INTERFACE
TCY(EN)
Enable Cycle Time
VDD = 4.5V; Write
125
ns
TW(EN)
Enable Pulse width
VDD = 4.5V; Write
60
ns
TSU(A)
Address Set-up Time
VDD = 4.5V; Write
30
ns
TH(A)
Address Hold Time
VDD = 4.5V; Write
50
ns
TSU(D)
Data Set-Up Time
VDD = 4.5V; Write
30
ns
TH(D)
Data Hold Time
VDD = 4.5V; Write
50
ns
SERIAL INTERFACE
FSCLK
Clock Frequency
VDD = 4.5V
8
MHz
VDD1 = 1.8V
5
MHz
TCYC
Clock Cycle SCLK
VDD = 4.5V
125
ns
TPWH1
SCLK pulse width HIGH
VDD = 4.5V
70
ns
TPWL1
SCLK Pulse width LOW
VDD = 4.5V
70
ns
TS2
SCE setup time
50
ns
TH2
SCE hold time
50
ns
TPWH2
SCE minimum high time
60
ns
TH5
SCE start hold time
Note 8
60
ns
TS3
SD/C setup time
60
ns
TH3
SD/C hold time
40
ns
TS4
SDIN setup time
40
ns
TH4
SDIN hold time
40
ns
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
F
frame
f
osc
520
----------
=
ELECTRICAL CHARACTERISTICS (continued)



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