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HC708KL8GRS/D Datasheet(PDF) 74 Page - NXP Semiconductors |
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HC708KL8GRS/D Datasheet(HTML) 74 Page - NXP Semiconductors |
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74 / 246 page ![]() System Integration Module (SIM) General Release Specification MC68HC708KL8 — Rev. 2.1 74 System Integration Module (SIM) Freescale Semiconductor 8.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.8.1 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.8.2 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.8.3 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . 97 8.2 Introduction This section describes the system integration module (SIM), which supports up to 16 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. The SIM is a system state controller that coordinates CPU and exception timing. A block diagram of the SIM is shown in Figure 8-1. Table 8-1 is a summary of the SIM I/O registers. The SIM is responsible for: • Bus clock generation and control for CPU and peripherals – Stop/wait/reset/break entry and recovery – Internal clock control • Master reset control, including power-on reset (POR) and COP timeout • Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation • CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources |
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