6.7

En/Fault pin

The EN/Fault pin has the dual function of controlling the output of the device and providing information about the

device status to the application.

When it is used as a standard Enable pin, it can be connected to an external open drain or open-collector device.

In this case, when it is pulled to a low logic level, it turns the output of the eFuse off.

High and low logic levels are defined as VIH and VIL in Table 5.

If this pin is left floating, since it has an internal pull-up circuitry, the eFuse is turned on.

Pull-up current is 20 µA clamped to 5 V (VI(MAX)).

On the STEF12S (latch version), in case of thermal fault, the pin is pulled to an intermediate state (VI(INT)) as

shown in Figure 6. En/Fault pin status. This signal can be provided to a monitor circuit, informing it that a thermal

shutdown has occurred, or it can be directly connected to the EN/Fault pins of other eFuse devices on the same

application in order to achieve a simultaneous enable/disable feature.

When a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the

Enable pin below the Vil threshold and then releasing it.

On the STEF12SA autoretry version, once the thermal shutdown is triggered, the EN/Fault pin of the device is set

to low state. It goes back to high level once the autoretry occurs.

Figure 6. En/Fault pin status

0

1

2

3

4

5

6

time

Device ON

Thermal fault

OFF/Reset

6.8

Reverse blocking function

Many applications require reverse current blocking, to allow the completion of pending system activities (such as

writing the data on SSD or parking the head in HDD) in case of power loss or during brownout. The STEF12S

provides a dedicated gate drive signal on the VG pin, which can be used to control an external blocking MOSFET,

M1 as shown in Figure 4. Application with external reverse current blocking MOSFET. As VCC drops during

input power removal, the signal on Vg falls, and both the internal pass element and M1 MOSFET are turned off,

therefore blocking any current flow from the load to the input of the eFuse. By appropriate selection of COUT the

required load current can be guaranteed to complete the power-down sequence.

6.9

Application suggestions and PCB layout guidelines

Input and output capacitors are mandatory to guarantee the device control loop stability and reduce the transient

effects of stray inductances, which may be present on the input and output power paths. In fact, when the

STEF12S interrupts the current flow, input inductance generates a positive voltage spike on the input, and output

inductance generates a negative voltage spike on the output.

To reduce the effects of such transients, a CIN capacitor of at least 1 μF (including voltage and temperature

derating) is recommended between the input pin and GND, and located as close as possible to the device.

STEF12S

En/Fault pin

DS13002 - Rev 5

page 10/31