List of figures

Figure 1.

Block diagram .................................................................... 2

Figure 2.

Pin connection (top view) ............................................................. 3

Figure 3.

Typical application circuit ............................................................. 4

Figure 4.

Application with external reverse current blocking MOSFET ..................................... 4

Figure 5.

Delay time and VOUT ramp-up time ...................................................... 8

Figure 6.

En/Fault pin status ................................................................ 10

Figure 7.

PCB layout example ............................................................... 11

Figure 8.

ILim and IShort vs. RLim - (STEF12SGR) .................................................. 12

Figure 9.

ILim and IShort vs. RLim - (STEF12SPUR) ................................................. 12

Figure 10.

Bias current vs. temperature.......................................................... 12

Figure 11.

Bias current vs. temperature (thermal shutdown)............................................ 12

Figure 12.

RDS_ON vs. temperature............................................................. 13

Figure 13.

ILIM vs. temperature ............................................................... 13

Figure 14.

IShort vs. temperature............................................................... 13

Figure 15.

Clamping voltage vs. temperature ...................................................... 13

Figure 16.

UVLO vs. temperature .............................................................. 13

Figure 17.

UVLO hysteresis vs. temperature ...................................................... 13

Figure 18.

En/Fault pin thresholds vs. temperature .................................................. 14

Figure 19.

En/Fault pull-up voltage vs. temperature ................................................. 14

Figure 20.

En/Fault pin current vs. temperature (En/Fault to GND) ....................................... 14

Figure 21.

Soft-start time vs. temperature (no Cdvdt) ................................................. 14

Figure 22.

Start-up via input voltage (no load) ..................................................... 14

Figure 23.

Start-up via En/Fault pin (no load) ..................................................... 14

Figure 24.

Start-up via input voltage (5 Ω load) .................................................... 15

Figure 25.

Start-up via input voltage (COUT = 1500 µF) ............................................... 15

Figure 26.

Start-up into voltage clamp........................................................... 15

Figure 27.

Voltage clamp during operation........................................................ 15

Figure 28.

Start-up into output short-circuit ....................................................... 15

Figure 29.

Start-up into overload .............................................................. 15

Figure 30.

Overcurrent protection during operation .................................................. 16

Figure 31.

Output short-circuit during operation .................................................... 16

Figure 32.

Thermal shutdown (latched version) .................................................... 16

Figure 33.

Thermal shutdown (autoretry version) ................................................... 16

Figure 34.

TSOT23-8L package outline.......................................................... 17

Figure 35.

TSOT23-8L recommended footprint .................................................... 19

Figure 36.

DFN10 (3 x 3 mm) package outline ..................................................... 20

Figure 37.

DFN10 (3 x 3 mm) recommended footprint ................................................ 21

Figure 38.

TSOT23-8L reel drawing outline ....................................................... 22

Figure 39.

TSOT23-8L carrier tape ............................................................. 23

Figure 40.

TSOT23-8L device orientation in tape ................................................... 23

Figure 41.

DFN10 (3 x 3 mm) reel drawing outline .................................................. 24

Figure 42.

DFN10 (3 x 3 mm) carrier tape ........................................................ 25

Figure 43.

DFN10 (3 x 3 mm) device orientation in tape .............................................. 25

STEF12S

List of figures

DS13002 - Rev 5

page 30/31