For the same reason, a COUT capacitor of at least 1 μF (including voltage and temperature derating) must be

connected to the output port.

When the device is powered by a power line made up of very long wires, the input inductance is higher than few

μH, so the input capacitor should be increased in order to guarantee the proper operation of the device.

It is suggested to provide for additional protections and methods to address these transients, such as:

•

Minimizing inductance of the input and output tracks

•

TVS diodes on the input to absorb inductive spikes

•

Schottky diode on the output to absorb negative spikes. The negative AMR of VOUT pin is - 0.3 V (see

Table 2.), nevertheless, negative transient up to - 0.6 V with a maximum duration of 50 μs are tolerated by

the device. Schottky diode must be selected to satisfy the above requirements.

•

Combination of ceramic and electrolytic capacitors on the input and output.

The PCB layout is critical for a stable and reliable operation. Refer to the typical PCB layout example shown in

Figure 7. PCB layout example and to the following guidelines:

•

Defining the high current input and output copper traces as short as possible and adequately sized to

sustain at least the overload current

•

Placing the RLim resistor close to the ILim pin and connect the other terminal of the component to VOUT with

the shortest possible trace. In fact, parasitic effects on the RLim connection trace can affect the current limit

accuracy.

•

Placing the Cdv/dt capacitor close to the dV/dt pin and connect the other terminal to GND with the shortest

possible trace. Use low-leakage components for Cdvdt.

•

The TSOT23-8L package dissipates the thermal power mainly through the leads, so providing large enough

copper areas around the PCB soldering pads is recommended.

Figure 7. PCB layout example

VOUT /Source

VCC

GND

Top layer

Bottom layer

STEF12S

Application suggestions and PCB layout guidelines

DS13002 - Rev 5

page 11/31