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X80121 Datasheet(PDF) 7 Page - Renesas Technology Corp |
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X80121 Datasheet(HTML) 7 Page - Renesas Technology Corp |
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7 / 17 page ![]() X80120, X80121 FN8151 Rev 0.00 Page 7 of 17 January 20, 2005 Symbol Table Pin Configuration FIGURE 5. WP, A0, A1, VP PIN TIMING tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte START WP VP tSU:VP tWC tHD:ADR tSU:ADR A1, A0 STOP SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition FIGURE 6. WRITE CYCLE TIMING Must be steady Will be steady May change from LOW Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known WAVEFORM INPUTS OUTPUTS to HIGH X80120/21 V1GDO DNC DNC V4MON VCC V1MON RESET WP V4GDO SCL 1 2 3 4 5 67 18 19 20 8 17 (5mm x 5mm) 910 11 12 14 15 16 13 |
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