X80120, X80121

FN8151 Rev 0.00

Page 8 of 17

January 20, 2005

Functional Description

Power On Reset and System Reset With Delay

Application of power to the X80120 activates a Power On

Reset circuit that pulls the RESET pin active. This signal, if

used, prevents the system microprocessor from starting to

operate while there is insufficient voltage on any of the

supplies. This circuit also does the following:

• It prevents the processor from operating prior to stabilization

of the oscillator.

• It allows time for an FPGA to download its configuration prior

to initialization of the circuit.

• It prevents communication to the EEPROM during unstable

power conditions, greatly reducing the likelihood of data

corruption on power up.

• It allows time for all supplies to turn on and stabilize prior to

system initialization.

The POR/RESET circuit is activated when all voltages are

within specified ranges and the V1GDO and V4GDO time-out

conditions are met. The POR/RESET circuit will then wait

tSPOR and de-assert the RESET pin. The POR delay may be

changed by setting the TPOR bits in register CR2. The delay

can be set to 100ms, 500ms, 1 second, or 5 seconds.

Pin Descriptions

PIN

NAME

DESCRIPTION

1V4GDO

V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than VREF4

and goes LOW when V4MON is greater than VREF4. There is user selectable delay circuitry on this pin.

2

V4MON

V4 Voltage Monitor Input. Second voltage monitor pin. If unused connect to VCC.

3

DNC

Do Not Connect

4VCC

Connect to VCC.

5

DNC

Do Not Connect.

6VP

EEPROM programming Voltage.

7VCC

Connect to VCC.

8

DNC

Do Not Connect.

9

A1

Address Select Input. It has an internal pull-down resistor. (>10M

 typical)

The A0 and A1 bits allow for up to 4 X80120 devices to be used on the same SMBus serial interface.

10

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and

may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input

buffer is always active (not gated).

11

SCL

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

12

V1MON

V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to VCC.

13

V1GDO

V1 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V1MON is less than VREF1

and goes LOW when V1MON is greater than VREF1. There is user selectable delay circuitry on this pin.

14

RESET

RESET Output. This open drain pin is an active LOW output. This pin will be active until all ViGDO pins go inactive and

the power sequencing is complete. This pin will be released after a programmable delay.

15

WP

Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the

device. It has an internal pull-down resistor. (>10M

 typical)

16

MR

Manual Reset. Pulling the MR pin HIGH initiates a RESET. The MR signal must be held HIGH for 5

secs. It has an

internal pull-down resistor. (>10M

 typical)

17

VSS

Ground Input.

18

NC

No Connect. No internal connections.

19

A0

Address Select Input. It has an internal pull-down resistor. (>10M

 typical) The A0 and A1 bits allow for up to 4

X80120 devices to be used on the same SMBus serial interface.

20

VCC

Supply Voltage.

TABLE 1. POR RESET DELAY OPTIONS

TPOR1

TPOR0

tSPOR DELAY BEFORE RESET

ASSERTION

0

0

100 miliseconds (default)

0

1

500 miliseconds

1

0

1 second

1

1

5 seconds