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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

16 Reference Clock

The differential reference clock (REF_CLK+/-) is used to generate the sRIO PHY and internal clocks used in the CPS-10Q. This is a CML-based differ-

ential input.

Reference Clock Electrical Specifications

The reference clock is 156.25 MHz, and is AC-coupled with the following electrical specifications:

Figure 18 REF_CLK Representative Circuit

The reference clock wander should not be more than 100ppm (for 156.25 MHz, this is +/-15.625 KHz). This requirement comes from the sRIO specifi-

cation that outgoing signals from separate links which belong to the same port should not be separated more than 100ppm. We recommend the

following device as reference clock device: ICS843001I-23 LVPECL, ICS8416641, ICS843256, ICS 87949, etc. Please contact IDT technical support

for further clock support.

Note that the series capacitors are discrete that must be placed external to the device’s receivers. All other elements are associated with the input

structure internal to the device. VBIAS is generated internally.

Name

Description

Min

Nom

Max

Units

REF_CLK

REF_CLK clock running at 156.25Mhz

-100

__

+100

ppm

Phase Jitter (rms)

Phase Jitter (rms) (1MHz - 20MHz)

__

__

2ps

tDUTY_REF

REF_CLK duty cycle

40

50

60

%

tRCLK/tFCLK

Input signal rise/fall time (20%-80%)

200

500

650

ps

vIN_CML

Differential peak-peak REF_CLK input swing

400

__

2400

mV

RL_CLK

Input termination resistance

40

50

60

ohm

LI_CLK

Input inductance

__

__

4nH

CI_CLK

Input capacitance

__

__

5pF

Table 28 Input Reference Clock Jitter Specifications

5686 drw07

REF_CLK_P

REF_CLK_N

REF_CLK

LI,CLK

CI,CLK

VBIAS,CLK

LI,CLK

CI,CLK

RL,CLK

RL,CLK

+

-

Internal

External

to Device

to Device