12 of 49

January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

11.2 Sustained Per-Port Throughput (Typical)

Notes:

1. Values are guaranteed by characterization, but are not production tested.

2. Throughput values are for 8bit destination ID packet, Header + Pay Load + CRC. The (Header + CRC) size changes depending on payload size. For payloads less

then 80 Bytes, the (Header + CRC) is 12 bytes. For payloads bigger than 80 Bytes, the (Header + CRC) is 14 bytes.

3. As payload size increases, the physical layer control symbols (sRIO required overhead) become a smaller percentage of the overall per-port throughput figure. The

physical layer symbols include one SoP and one EoP for every packet. There is a status control symbol for every 1024 transmitted code-group as well as synchro-

nization sequences required by sRIO. For two way traffic, packet acknowledgment control symbols will occur between the packets.

11.3 Data Packet Latency in “Store-and-Forward” Mode (Typical)

Notes:

1. Values are guaranteed by characterization, but are not production tested.

2. For those specifications associated with an sRIO transaction, it should be noted that the upper limit to a specification may be dictated by sRIO priority handling. For

example, a maintenance read packet having lower priority may be held off until higher priority packets in queue are serviced. The user should take into consider-

ation this additional priority-induced delay when examining these specifications. I2C and JTAG transactions are always deterministic and follow these specifications

identically.

3. Switch latency is a statistical function, which typically increases with increased traffic loading on the switch. Values shown in Table 6 are typical for single input port

to single output port with matching input and output port rates in “Store-and-Forward” mode, no other switch loading. The switch latency in “Store-and-Forward”

packet forward methodology is also a strong function of port rate. For specific values under other specific application usage scenarios and traffic conditions, please

contact IDT technical support.

Pay Load Size

1.25GHz

2.5GHz

3.125GHz

1X

4X

1X

4X

1X

4X

16 Byte

0.70 G

2.33 G

1.38 G

4.42 G

1.93 G

4.67

32 Byte

0.79 G

2.4 G

1.57 G

5.48 G

2.1 G

5.89

64 Byte

0.86 G

2.92 G

1.73 G

6.32 G

2.24 G

7.02 G

128 Byte

0.94 G

3.38 G

1.87 G

6.76 G

2.28 G

8.19 G

256 Byte

0.97 G

3.66 G

1.93 G

7.30 G

2.39 G

8.93 G

Table 5 Sustained Per-Port Throughput (Typical)

Pay Load Size

1.25GHz

2.5GHz

3.125GHz

1X

4X

1X

4X

1X

4X

8 Byte

454 ns

328 ns

271 ns

228 ns

240 ns

211 ns

16 Byte

518 ns

348 ns

304 ns

234 ns

266 ns

216 ns

32 Byte

646 ns

380 ns

367 ns

246 ns

316 ns

227 ns

64 Byte

905 ns

441 ns

493 ns

271 ns

419 ns

253 ns

128 Byte

1449 ns

580 ns

770 ns

336 ns

641 ns

307 ns

256 Byte

2473 ns

833 ns

1282 ns

457 ns

1049 ns

409 ns

Multicast Event

Control Symbol

126 ns

115 ns

66 ns

60 ns

55 ns

49 ns

Table 6 Switch Latency Table (Store-and-Forward Mode, Typical)