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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

JTAG Timing Waveforms

Figure 27 JTAG Timing Specifications

Notes:

1. Device inputs = All device inputs except TDI, TMS, and TRST.

2. Device outputs = All device outputs except TDO.

18 Reset & Initialization

Power Supply Sequencing

The CPS-10Q does not require specific power sequencing between any of the core and I/O supplies.

Reset Pin and Timing

Figure 28 Reset Timing

To reset the device, first reset signal has to be de-asserted (Reset Low), and it is asserted after 5 REF_CLK cycles. 4096 REF_CLK cycles later, the

device completes the reset process. Once completed, access to the CPS-10Q from any and all interfaces is possible and the device is fully functional.

Control and data traffic will not be accepted by the CPS-10Q until this process is fully completed.

TCK

Device Inputs(1)/

TDI/TMS

Device Outputs(2)/

TDO

TRST

tJCD

tJDC

tJRST

tJS

tJH

tJCYC

tJRSR

tJF

tJCL

tJR

tJCH

5686 drw 08

,

RST

5 REF_CLK Cycles

4096 REF_CLK Cycles