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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

Signaling

Communication with the CPS-10Q on the I2C bus follows these three cases:

1) Suppose a master device wants to send information to the CPS-10Q:

– Master device addresses CPS-10Q (slave)

– Master device (master-transmitter), sends data to CPS-10Q (slave- receiver)

– Master device terminates the transfer

2) If a master device wants to receive information from the CPS-10Q:

– Master device addresses CPS-10Q (slave)

– Master device (master-receiver) receives data from CPS-10Q (slave- transmitter)

– Master device terminates the transfer.

3) If CPS-10Q polls configuration image from external memory

– CPS-10Q addresses the memory.

– Memory transmits the data.

– CPS-10Q gets the data.

All signaling is fully compliant with I2C. Full detail of signaling can be found in the Philips I2C specification [1]. Standard signaling and timing

waveforms are shown below.

Interfacing to Standard-, Fast-, and Hs-mode Devices

The CPS-10Q supports Fast / Standard (F/S) modes of operation. Per I2C specification, in mixed speed communication the CPS-10Q supports Hs-

and Fast-mode devices at 400 kbit/s, and Standard-mode devices at 100 kbit/s. Please refer to the I2C specification for detail on speed negotiation on

a mixed speed bus.

CPS-10Q-Specific Memory Access (Slave mode)

There is a CPS-10Q-specific I2C memory access implementation. This implementation is fully I2C compliant. It requires the memory address to be

explicitly specified during writes. This provides directed memory accesses through the I2C bus. Subsequent reads always begin at the address speci-

fied during the last write.

The write procedure requires the 3-Bytes (22-bits) of memory address to be provided following the device address. Thus, the following are required:

device address – one or two bytes depending on 10-bit / 7-bit addressing, memory address – 3 bytes yielding 22-bits of memory address, and a 32-bit

data payload – 4 byte words. To remain consistent with sRIO standard maintenance packet memory address convention, the I2C memory address

provided must be the 22MSBs. Since I2C writes to memory apply to double words (32-bits), the 2 LSBs are DON’T CARE as the LSBs correspond to

word and byte pointers.

The read procedure has the memory address section of the transfer removed. Thus, to perform a read, the proper access would be to perform a write

operation and issue a repeated start after the acknowledge bit following the third byte of memory address. Then, the master would issue a read

command selecting the CPS-10Q through the standard device address procedure with the R/W bit high. Note that in 10-bit device address mode

(ADS=1), only the two MSBs need be provided during this read. Data from the previously loaded address would immediately follow the device address

protocol. It is possible to issue a stop or repeated start anytime during the write data payload procedure, but must be before the final acknowledge (i.e.

canceling the write before the actual write operation is completed and performed). Also, the master would be allowed to access other devices attached

to the I2C bus before returning to select the CPS-10Q for the subsequent read operation from the loaded address.