26

5387B–HIREL–07/05

PC7447A [Preliminary]

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) fre-

quency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum

PLL_CFG[0:4] settings.

2. Assumes a lightly-loaded, single-processor system.

3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V.

4. Timing is guaranteed by design and characterization.

5. Guaranteed by design.

6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at -3 dB.

7. Relock timing is guaranteed by design and characterization. PLL relock time is the maximum amount of time required for

PLL lock after a stable V

when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held

asserted for a minimum of 255 bus clocks after the PLL relock time during the power-on reset sequence.

8. Caution: If DFS is enabled, the SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting pro-

cessor frequency is greater than or equal to the minimum core frequency.

9. Caution: These values specify the maximum processor core and VCO frequencies when the device is operated at the nomi-

nal core voltage. If operating the device at the derated core voltage, the processor core and VCO frequencies must be

reduced.

Figure 9-1.

SYSCLK Input Timing Diagram

V

9.2.2

Processor Bus AC Specifications

Symbol

Characteristic

Maximum Processor Core Frequency

Unit

Notes

1000 MHz

1167 MHz

Min

Max

Min

Max

f

CORE

Processor core frequency

500

1000

500

1167

MHz

(1)(8)(9)

VCO frequency

1000

2000

1000

2233

MHz

(1)(9)

SYSCLK frequency

33

167

33

167

MHz

(1)(2)(8)

t

SYSCLK

SYSCLK cycle time

6

30

6

30

ns

(2)

SYSCLK rise and fall time

–

1

–

1

ns

(3)

40

60

40

60

%

(4)

–150–150

ps

(5)(6)

–100–100

µs

(7)

SYSCLK

VM

VM

VM

tKHKL

tSYSCLK

CVIL

CVIH

tKR

tKF