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UPD17062 Datasheet(PDF) 81 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 81 Page - Renesas Technology Corp |
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81 / 298 page  79 µPD17062 9.9 PLL REFERENCE MODE SELECTION REGISTER (13H) 9.10 SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H) b3 b2 b1 b0 PLLRFCK3 PLLRFCK2 PLLRFCK0 13H PLLRFCK1 00 1 0 00 1 1 01 1 0 11 1 1 01 1 1 10 1 0 10 1 1 11 1 0 6.25 kHz 12.5 kHz 25 kHz PLL disabled Not to be set Reference frequency fr setting Fixed at 1 b3 b2 b1 b0 INTNCMD3 INTNCMD2 INTNCMD0 15H INTNCMD1 00 0 00 1 01 0 01 1 10 0 Edge (no noise canceler) 200 s 2 ms Setting of INTNC pin acceptance pulse width Fixed at 0 4 ms 400 s µ µ |
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