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UPD17062 Datasheet(PDF) 83 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 83 Page - Renesas Technology Corp |
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83 / 298 page  81 µPD17062 b3 b2 b1 b0 ADCCH2 ADCCH1 ADCCMP 21H ADCCH0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1 ADC0 select ADC1 select, shared with P1C3 ADC2 select, shared with P0D0 ADC3 select, shared with P1D1 ADC4 select, shared with P0D2 ADC5 select, shared with P0D3 No corresponding channel (not to be set) A/D converter input channel select 9.14 A/D CONVERTOR CONTROL (21H) 9.15 PLL UNLOCK FLIP-FLOP JUDGE REGISTER (22H) b3 b2 b1 b0 0 0 PLLUL 22H 0 1 0 Detects the unlock flip-flop state Unlock flip-flop = 0: PLL locked Unlock flip-flop = 1: PLL unlocked |
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