UPD17062 datasheet(96/298 Pages) RENESAS

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µPD17062

Table 10-1

Peripheral Hardware and Data Buffer Functions

Data buffer and data transfer

Function

peripheral register

Peripheral hardware

Name

Symbol

Peri-

PUT

Data

Valid

Explanation

pheral instruction/

buffer

bits

address

GET

I/O bits

instruction

Image display

IDC start posi- IDCORG

01H

PUT/GET

Sets the image display

controller

tion setting

controller display start

position.

A/D converter

ADCR

02H

PUT/GET

Sets the AD converter

VREF data

comparison voltage

VREF.

VREF =

x – 0.5

× VDD (V)

≤ x ≤ 15

Serial interface

Presettable

SIO0SFR

03H

PUT/GET

Sets the serial out data

shift register

and reads the serial in

data.

Horizontal syn-

HSYNC

HSC

04H

GET

Reads the value of the

chronizing signal

counter data

horizontal synchroni-

counter

zing signal counter.

PWM0

PWM data

PWMR0

05H

PUT/GET

Sets the D/A converter

output signal duty.

PWM1

PWM data

PWMR1

06H

Duty D =

x + 0.75

(%)

PWM2

PWM data

PWMR2

07H

≤ x ≤ 63

Frequency f = 15.625 kHz

PWM3

PWM data

PWMR2

08H

Address register

Address

40H

PUT/GET

Reads of writes data

from or to the address

PLL frequency

PLL data

PLLR

41H

PUT/GET

Sets the PLL frequency

synthesizer

synthesizer frequency

division ratio.

6-bit

D/A

conver-

ter

(PWM

output)

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