MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC93R52/D

Rev 2, 04/2003

1

3.3V 1:11 LVCMOS Zero Delay

Clock Generator

The MPC93R52 is a 3.3V compatible, 1:11 PLL based clock generator

targeted for high performance clock tree applications. With output

frequencies up to 240 MHz and output skews lower than 200 ps the

device meets the needs of most demanding clock applications.

Features

2

B3, 1B3 and 1B2

applications

Functional Description

The MPC93R52 is a fully 3.3V compatible PLL clock generator and

clock driver. The device has the capability to generate output clock

signals of 16.67 to 240 MHz from external clock sources. The internal PLL

optimized for its frequency range and does not require external look filter

components. One output of the MPC93R52 has to be connected to the

PLL feedback input FB_IN to close the external PLL feedback path. The

output divider of this output setting determines the PLL frequency

multiplication factor. This multiplication factor, F_RANGE and the

reference clock frequency must be selected to situate the VCO in its

specified lock range. The frequency of the clock outputs can be

configured individually for all three output banks by the FSELx pins

supporting systems with different but phase-aligned clock frequencies.

The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and

outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50

Ω transmission lines. Alternatively,

each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.

The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The

MPC93R52 is package in a 32 ld LQFP.

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

MPC93R52

LOW VOLTAGE

3.3V LVCMOS 1:11

CLOCK GENERATOR