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AT89C51CC02CA-RATUM Datasheet(PDF) 30 Page - ATMEL Corporation |
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AT89C51CC02CA-RATUM Datasheet(HTML) 30 Page - ATMEL Corporation |
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30 / 156 page  30 AT/T89C51CC02 4126J–CAN–05/06 Table 19. AUXR1 Register AUXR1 (S:A2h) Auxiliary Control Register 1 Reset Value = XXXX 00X0b Note: 1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming section. 76 54 32 1 0 - - ENBOOT - GF3 0 - DPS Bit Number Bit Mnemonic Description 7 - 6 - Reserved The value read from these bits is indeterminate. Do not set these bits. 5ENBOOT (1) Enable Boot Flash Set this bit to map the boot Flash between F800h -FFFFh Clear this bit to disable boot Flash. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3GF3 General Purpose Flag 3 20 Always Zero This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. 1- Reserved for Data Pointer Extension 0DPS Data Pointer Select bit Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0. |
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