AT89C51CC02CA-RATUM datasheet(58/156 Pages) ATMEL

58 / 156 page

AT/T89C51CC02

4126J–CAN–05/06

Mode 0 (13-bit Timer)

Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0

(See Figure 24). The upper three bits of TL0 register are indeterminate and should be

ignored. Prescaler overflow increments TH0 register.

Figure 24. Timer/Counter x (x= 0 or 1) in Mode 0

Mode 1 (16-bit Timer)

Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in

cascade (See Figure 25). The selected input increments TL0 register.

Figure 25. Timer/Counter x (x= 0 or 1) in Mode 1

Mode 2 (8-bit Timer with Auto-

Reload)

Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

from TH0 register (See Figure 26). TL0 overflow sets TF0 flag in TCON register and

reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next

reload value may be changed at any time by writing it to TH0 register.

FTx

CLOCK

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

÷ 6

Overflow

Timer x

Interrupt

Request

C/Tx#

TMOD Reg

TLx

(5 bits)

THx

(8 bits)

INTx#

See section “Clock”

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

Overflow

Timer x

Interrupt

Request

C/Tx#

TMOD Reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FTx

CLOCK

÷ 6

See section “Clock”

AT89C51CC02CA-RATUM Datasheet(PDF) 58 Page - ATMEL Corporation

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