AT89C5132-ROTIL datasheet(35/181 Pages) ATMEL

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4173D–USB–02/06

AT89C5132

Table 33. Priority Levels

A low-priority interrupt is always interrupted by a higher priority interrupt but not by another inter-

rupt of lower or equal priority. Higher priority interrupts are serviced before lower priority

interrupts. The response to simultaneous occurrence of equal priority interrupts is determined by

an internal hardware polling sequence detailed in Table 34. Thus within each priority level there

is a second priority structure determined by the polling sequence. The interrupt control system is

shown in Figure 10-1.

Table 34. Priority Within Same Level

IPHxx

IPLxx

Priority Level

0 Lowest

3 Highest

Interrupt Name

Priority Number

Interrupt Address Vectors

Interrupt Request Flag

Cleared by Hardware (H)

or by Software (S)

INT0

0 (Highest Priority)

C:0003h

H if edge, S if level

Timer 0

C:000Bh

INT1

C:0013h

H if edge, S if level

Timer 1

C:001Bh

Serial Port

C:0023h

Reserved

Audio Interface

C:0033h

MMC Interface

C:003Bh

Two-wire Controller

C:0043h

SPI Controller

C:004Bh

A-to-D Converter

C:0053h

Keyboard

C:005Bh

Reserved

C:0063h

USB

C:006Bh

Reserved

14 (Lowest Priority)

C:0073h

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