AT89C5132-ROTIL datasheet(57/181 Pages) ATMEL

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4173D–USB–02/06

AT89C5132

13. Watchdog Timer

The AT89C5132 implement a hardware Watchdog Timer (WDT) that automatically resets the

chip if it is allowed to time out. The WDT provides a means of recovering from routines that do

not complete successfully due to software or hardware malfunctions.

13.1

Description

The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in

Figure 13-1, the 14-bit prescaler is fed by the WDT clock detailed in section "Watchdog Clock

Controller", page 57.

The Watchdog Timer Reset register (WDTRST, see Table 47) provides control access to the

WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 48) provides time-out

period programming.

Three operations control the WDT:

•

Chip reset clears and disables the WDT.

•

Programming the time-out value to the WDTPRG register.

•

Writing a specific two-byte sequence to the WDTRST register clears and enables the WDT.

Figure 13-1. WDT Block Diagram

13.2

Watchdog Clock Controller

As shown in Figure 13-2 the WDT clock (F

WDT) is derived from either the peripheral clock (FPER)

or the oscillator clock (F

OSC) depending on the WTX2 bit in CKCON register. These clocks are

issued from the Clock Controller block as detailed in section "Clock Controller", page 12. When

WTX2 bit is set, the WDT clock frequency is fixed and equal to the oscillator clock frequency

divided by 2. When cleared, the WDT clock frequency is equal to the oscillator clock frequency

divided by 2 in standard mode or to the oscillator clock frequency in X2 mode.

Figure 13-2. WDT Clock Controller and Symbol

WTO2:0

WDTPRG.2:0

WDT

CLOCK

÷ 6

System

1Eh-E1h Decoder

WDTRST

14-bit Prescaler

RST

7-bit Counter

RST

To internal

RST

MATCH

SET

OSC

CLOCK

RST

Pulse Generator

Reset

reset

PER

CLOCK

WDT

CLOCK

OSC

CLOCK

WTX2

CKCON.6

÷ 2

WDT Clock

WDT Clock Symbol

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