AT89C5132-ROTUL datasheet(77/181 Pages) ATMEL

77 / 181 page

4173D–USB–02/06

AT89C5132

Reset Value = 0000 0000b

Table 63. UEPRST Register

UEPRST (S:D5h) – USB Endpoint FIFO Reset Register

Bit

Number

Bit

Mnemonic Description

7DIR

Control Endpoint Direction Bit

This bit is relevant only if the endpoint is configured in Control type.

Set for the data stage. Clear otherwise.

Note: This bit should be configured on RXSETUP interrupt before any other bit is

changed. This also determines the status phase (IN for a control write and OUT

for a control read). This bit should be cleared for status stage of a Control Out

transaction.

Reserved

The values read from this Bits are always 0. Do not set this bit.

STALLRQ

Stall Handshake Request Bit

Set to send a STALL answer to the host for the next handshake.Clear otherwise.

TXRDY

TX Packet Ready Control Bit

Set after a packet has been written into the endpoint FIFO for IN data transfers.

Data shall be written into the endpoint FIFO only after this bit has been cleared.

Set this bit without writing data to the endpoint FIFO to send a Zero Length

Packet, which is generally recommended and may be required to terminate a

transfer when the length of the last data packet is equal to MaxPacketSize (e.g.,

for control read transfers).

Cleared by hardware, as soon as the packet has been sent for Isochronous

endpoints, or after the host has acknowledged the packet for Control, Bulk and

Interrupt endpoints.

3STLCRC

Stall Sent Interrupt Flag/CRC Error Interrupt Flag

For Control, Bulk and Interrupt Endpoints:

Set by hardware after a STALL handshake has been sent as requested by

STALLRQ. Then, the endpoint interrupt is triggered if enabled in UEPIEN.

Cleared by hardware when a SETUP packet is received (see RXSETUP).

For Isochronous Endpoints:

Set by hardware if the last data received is corrupted (CRC error on data). Then,

the endpoint interrupt is triggered if enabled in UEPIEN.

Cleared by hardware when a non corrupted data is received.

RXSETUP

Received SETUP Interrupt Flag

Set by hardware when a valid SETUP packet has been received from the host.

Then, all the other Bits of the register are cleared by hardware and the endpoint

interrupt is triggered if enabled in UEPIEN.

Clear by software after reading the SETUP data from the endpoint FIFO.

1RXOUT

Received OUT Data Interrupt Flag

Set by hardware after an OUT packet has been received. Then, the endpoint

interrupt is triggered if enabled in UEPIEN and all the following OUT packets to

the endpoint are rejected (NACK’ed) until this bit is cleared. However, for Control

endpoints, an early SETUP transaction may overwrite the content of the endpoint

FIFO, even if its Data packet is received while this bit is set.

Clear by software after reading the OUT data from the endpoint FIFO.

0TXCMP

Transmitted IN Data Complete Interrupt Flag

Set by hardware after an IN packet has been transmitted for Isochronous

endpoints and after it has been accepted (ACK’ed) by the host for Control, Bulk

and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled in

UEPIEN.

Clear by software before setting again TXRDY.

543

210

EP3RST

EP2RST

EP1RST

EP0RST

AT89C5132-ROTUL Datasheet(PDF) 77 Page - ATMEL Corporation

AT89C5132-ROTUL Datasheet(HTML) 77 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL