AT89C5132-ROTUL datasheet(97/181 Pages) ATMEL

97 / 181 page

4173D–USB–02/06

AT89C5132

The interrupt request is generated each time an unmasked flag is set, and the global MMC con-

troller interrupt enable bit is set (EMMC in IEN1 register).

Reading the MMINT register automatically clears the interrupt flags (acknowledgment). This

implies that register content must be saved and tested interrupt flag by interrupt flag to be sure

not to overlook any interrupts.

Figure 16-20. MMC Controller Interrupt System

16.8

Registers

Table 78. MMCON0 Register

MMCON0 (S:E4h) – MMC Control Register 0

MMC Interface

Interrupt Request

MCBI

MMINT.7

EOCM

MMMSK.5

EMMC

IEN1.0

MCBM

MMMSK.7

EORM

MMMSK.6

EOFI

MMINT.4

F2FM

MMMSK.3

EOFM

MMMSK.4

EORI

MMINT.6

F2FI

MMINT.3

EOCI

MMINT.5

F2EM

MMMSK.1

F1FM

MMMSK.2

F1EI

MMINT.0

F1EM

MMMSK.0

F1FI

MMINT.2

F2EI

MMINT.1

543

210

DRPTR

DTPTR

CRPTR

CTPTR

MBLOCK

DFMT

RFMT

CRCDIS

Bit

Number

Bit

Mnemonic

Description

7DRPTR

Data Receive Pointer Reset Bit

Set to reset the read pointer of the data FIFO.

Clear to release the read pointer of the data FIFO.

AT89C5132-ROTUL Datasheet(PDF) 97 Page - ATMEL Corporation

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