Data Sheet

8.6 GND, Ground

The GND pin is the ground connection for the digital and analog circuits in the AMIS-52100.

8.7 CLKOUT, Internal Clock Output

The CLKOUT pin is an output for the RC oscillator, crystal oscillator signal or the recovered data clock. The crystal oscillator signal

output can be divided by 2, 3 or 4. The pin can also be programmed to output the signal from the recovered data clock function. For

more information about the clock and data recovery (CDR) function of the AMIS-52100, refer to the section of this document on clock

and data recovery.

The CLKOUT pin function control registers are shown in Table 13.

Table 13: Oscillator Output Control Registers

CLKOUT Pin Definition Control Registers

Register (HEX)

Name

Bits

States

Comments

0x0c

CLKOUT enable

7

0

CLKOUT is enabled

1

CLKOUT is disabled

0x0d

CLKOUT select

4,5

00

Automatic control

01

RC OSC

10

Xtal

11

Off

0x0e

XTAL divide

0,1

00

Divide by 4

01

Divide by 3

10

Divide by 2

11

Divide by 1

8.8 X1, X2, External Crystal Reference

X1 and X2 pins connect a parallel resonance oscillator crystal to the AMIS-52100 internal oscillator circuit. The external crystal should

meet the requirements as listed in Table 14, however, the two load capacitors should be sized slightly smaller than the recommended

value for the crystal, because the AMIS-52100 adds capacitance in the internal trim circuit. For additional information, see the AMIS

Application Note; “Quick Start Crystal Oscillator Circuit Operation and Setup”. The crystal parameters are shown in Table 14.

Table 14: External Crystal Parameters

Parameter

Min.

Typ.

Max.

Units

Conditions

Crystal Frequency

12.56

12.65

MHz

Targeted

10.9

14.0

Non Quick Start

9.375

24.0

Using Quick Start

Crystal ESR

70

Ω

Crystal Tolerance

10

ppm

Load Capacitance

Load capacitors should be smaller than recommended for

the crystal to allow for frequency tune

8.9 I

The AMIS-52100 implements an I

implements the protocol for a slave device. The clock for the interface is generated by the external master device. The interface will

support the normal (0 – 100 Kbits/second) or the fast (0 – 400Kbits/second) data modes. The interface conforms to the Phillips

specification for the I

interface.

Table 17 shows the register that controls the I

9

AMI Semiconductor – Rev 4.0, Mar. 06 – M-20535-004

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