FALXT972MCCA4 datasheet(66/92 Pages) INTEL

66 / 92 page

Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

Figure 23 does not show the TX_ER signal.

Figure 23. Intel® LXT972M Transceiver 100BASE-TX Transmit Timing

0ns

250ns

TXCLK

TX_EN

TXD[3:0]

TPO

CRS

B3454-03

Note: Timing diagram depicts 4B mode.

Table 31. Intel® LXT972M Transceiver 100BASE-TX Transmit Timing Parameters

Parameter

Symbol

Min

Typ

Max

Units2

Test Conditions

TXD[3:0], TX_EN setup to TX_CLK

High

–

TXD[3:0], TX_EN hold from TX_CLK

High

–

TX_EN sampled to CRS asserted

–

TX_EN sampled to CRS de-asserted

–

TX_EN sampled to TPO out (Tx

latency)

5.3

–

5.7

–

1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production

testing.

2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit

rate. 100BASE-T bit time = 10-8 s or 10 ns.

FALXT972MCCA4 Datasheet(PDF) 66 Page - Intel Corporation

FALXT972MCCA4 Datasheet(HTML) 66 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL