 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
FALXT972MCCA4 Datasheet(PDF) 68 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
FALXT972MCCA4 Datasheet(HTML) 68 Page - Intel Corporation |
|
|
68 / 92 page  Intel ® LXT972M Single-Port 10/100 Mbps PHY Transceiver 68 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Figure 25. Intel® LXT972M Transceiver 10BASE-T Transmit Timing Table 33. Intel® LXT972M Transceiver 10BASE-T Transmit Timing Parameter Symbol Min Typ 1 Max Units2 Test Conditions TXD, TX_EN, setup to TX_CLK High t1 10 – – ns – TXD, TX_EN, hold from TX_CLK High t2 0 – – ns – TX_EN sampled to CRS asserted t3 – 2 – BT – TX_EN sampled to CRS de-asserted t4 – 1 – BT – TX_EN sampled to TPO out (Tx latency) t5 – 72.5 – BT – 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. 2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10 -7 s or 100 ns. TX_CLK TXD, TX_EN CRS TPO t1 t3 t4 t5 t2 B3461-01 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
