FALXT972MCCA4 datasheet(67/92 Pages) INTEL

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Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

Figure 24. Intel® LXT972M Transceiver 10BASE-T Receive Timing

Table 32. Intel® LXT972M Transceiver 10BASE-T Receive Timing

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

RXD, RX_DV. Setup to RX_CLK High.

–

RXD, RX_DV, RX_ER Hold from

RX_CLK High

–

TPIP/N in to RXD out (Rx latency)

4.2

–

6.6

–

CRS asserted to RXD, RX_DV,

RX_ER asserted

–

RXD, RX_DV, RX_ER de-asserted to

CRS de-asserted

0.3

–

0.5

–

TPI in to CRS asserted

–

TPI quiet to CRS de-asserted

–

TPI in to COL asserted

–

TPI quiet to COL de-asserted

–

1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production

testing.

2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit

rate. 10BASE-T bit time = 10-7 s or 100 ns.

RX_CLK

RXD,

RX_DV,

RX_ER

CRS

TPI

COL

B3457-01

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