FALXT972MCCA4 datasheet(71/92 Pages) INTEL

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Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

Figure 28. Intel® LXT972M Transceiver Auto-Negotiation and Fast Link Pulse Timing

Figure 29. Intel® LXT972M Transceiver Fast Link Pulse Timing

Table 36. Intel® LXT972M Transceiver Auto-Negotiation / Fast Link Pulse Timing

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Clock/Data pulse width

–

100

–

Clock pulse to Data pulse

55.5

–

63.8

μs–

Clock pulse to Clock pulse

123

–

127

μs–

FLP burst width

–

FLP burst to FLP burst

–

Clock/Data pulses per burst

–

Each clock

pulse or data

pulse

–

1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production

testing.

TPOP

Clock Pulse

Data Pulse

Clock Pulse

B3464-01

FLP Burst

TPOP

B3465-01

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