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FT2232D Datasheet(PDF) 35 Page - Future Technology Devices International Ltd. |
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FT2232D Datasheet(HTML) 35 Page - Future Technology Devices International Ltd. |
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35 / 56 page  DS2232D Version 0.91 © Future Technology Devices International Ltd. 2006 Page 35 of 51 FT2232D Dual USB UART / FIFO I.C. 25 FIFO Mode TIMING DIAGRAMS Figure 19 - FIFO READ Cycle Time Description Min Max Unit T1 RD# Active Pulse Width 50 ns T2 RD# to RD Pre-Charge Time 50 + T6 ns T3 RD# Active to Valid Data ** Note 19 20 50 ns T4 Valid Data Hold Time from RD# Inactive ** Note 19 0 ns T5 RD# Inactive to RXF# 0 25 ns T6 RXF# inactive after RD# cycle 80 ns ** Note 19 : Load 30 pF at standard drive level. These times will also vary if the high output drive level is enabled. Figure 20 - FIFO Write Cycle Time Description Min Max Unit T7 WR Active Pulse Width 50 ns T8 WR to WR Pre-Charge Time 50 ns T9 Data Setup Time before WR inactive 20 ns T10 Data Hold Time from WR inactive 0 ns T11 WR Inactive to TXE# 5 25 ns T12 TXE inactive after WR cycle 80 ns RXF# RD# D[7...0] T3 T1 T5 T6 T2 T4 Valid Data Valid Data D[7...0] WR TXE# T7 T12 T11 T8 T9 T10 |
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