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CS8420-CSZ Datasheet(PDF) 61 Page - Cirrus Logic |
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CS8420-CSZ Datasheet(HTML) 61 Page - Cirrus Logic |
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61 / 94 page  DS245F4 61 CS8420 13.3.1 Pin Description - Hardware Mode 2 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to VD+ in Hardware mode 2, in order to select the serial audio input. SFMT0, SFMT1 - Serial Audio Port Data Format Select Inputs SFMT0 and SFMT1 select the serial audio input and output ports’ format. See Table 10. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso). Audio Input Interface: SDIN - Serial Audio Input Port Data Input Audio data serial input pin. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi) |
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