PLL1707

PLL1708

SLES065 – DECEMBER 2002

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9

THEORY OF OPERATION

MASTER CLOCK AND SYSTEM CLOCK OUTPUT

The PLL1707/8 consists of a dual PLL clock and master clock generator which generates four system clocks and two

buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1707/8. The PLL is

designed to accept a 27-MHz master clock.

PLL2

Counter N

Phase Detector

and

Loop Filter

OSC

Divider

SCKO3

384 fS

SCKO0–3

Frequency

Control

Counter M

VCO

Divider

PLL1

Counter M

Phase Detector

and

Loop Filter

Counter N

VCO

SCKO2

256 fS

Divider

SCKO1

36.864/24.576 MHz

(36.864/24.576 MHz)

(18.432/12.288 MHz)

SCKO0

33.8688 MHz

MCKO2

27 MHz

MCKO1

27 MHz

XT1 XT2

( ): PLL1708

Figure 7. Block Diagram