PLL1707

PLL1708

SLES065 – DECEMBER 2002

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12

SCKO0

150 ns

SCKO1

SCKO2

SCKO3

FS2, 1

Stable

Clock Transition Region

Stable

33.8688 MHz

SR

CSEL

50 ns

Figure 11. SCKO Transient Timing

POWER-ON RESET

The PLL1707/8 has an internal power-on reset circuit. The mode register of the PLL1708 is initialized with default settings

by power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power-up time.

Initialization by internal power-on reset is done automatically during 1024 master clocks at VDD > 2.0 V (TYP). Power-on

reset timing is shown in Figure 12.

Reset

Reset Removal

1024 Master Clocks

VDD

2.4 V

2.0 V

1.6 V

Internal Reset

Master Clock

Figure 12. Power-On Reset Timing