PLL1707

PLL1708

SLES065 – DECEMBER 2002

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10

The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to

XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options,

and Figure 9 illustrates the 27-MHz master clock timing requirement.

Crystal

PLL1707/PLL1708

Crystal

OSC

Circuit

27-MHz

Internal

Master

Clock

XT1

XT2

C2

C1

MCKO1

MCKO2

C1, C2 = 10 pF to 33 pF

Crystal Resonator Connection

PLL1707/PLL1708

XT1

XT2

MCKO1

MCKO2

External Clock Input Connection

External

Clock

Crystal

OSC

Circuit

27-MHz

Internal

Master

Clock

Figure 8. Master Clock Generator Connection Diagram

t(XT1H)

XT1

t(XT1L)

0.7 VCC

0.3 VCC

DESCRIPTION

SYMBOL

MIN

MAX

UNIT

Master clock pulse duration HIGH

t(XT1H)

10

ns

Master clock pulse duration LOW

t(XT1L)

10

ns

Figure 9. External Master Clock Timing Requirement

The PLL1707/8 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs

256 fS, 384 fS 512 fS, or 768 fS (fS = 48 kHz) which is selected by hardware or software control. The output frequency of

the remaining clocks is determined by the sampling frequency (fS) under hardware or software control. SCKO2 and SCKO3

output 256-fS and 384-fS system clocks, respectively. Table 2 shows each sampling frequency which can be programmed.

The system clock output frequencies for programmed sampling frequencies are shown in Table 3. The half sampling

frequencies on SCKO2 and SCKO3 and 256 fS and 384 fS on SCKO1 are supported only on the PLL1708.

Table 1. Generated System Clock SCKO1 Frequency

fS

SCKO1 FREQUENCY

256 fS†

12.288 MHz

384 fS†

18.432 MHz

512 fS

24.576 MHz

768 fS

36.864 MHz

† PLL1708 only