L9848

Functional description

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3.2.2

Output 5-6

These two self-configuring outputs can be used to drive either high or low side loads. In

addition to be controlled by the SPI BUS these outputs can also be enabled and disabled via

IN5 and IN6 inputs. IN5 and IN6 inputs are logically ORed with the SPI commands to allow

either the IN5-6 inputs or the SPI commands to activate these outputs. The use of IN5-6 for

PWM control on these outputs should only be done with non-inductive loads. Integrated

current source pull-ups and pull-downs are employed to correctly latch "open load" fault

data. Both of these current sources are needed to detect an open since these outputs self

configure as either high or low side drives.

Drain connections of Output5-6 (DRN5-6)

These pins are connected to the drains of the n-channel MOSFET transistors.

Source connections of Output5-6 (SRC5-6)

These pins are connected to the sources of the n-channel MOSFET transistors.

3.2.3

Output7-8

These two outputs (DRN7-8) are dedicated low side drives. Integrated current source pull

down are required to correctly latch "open load" fault data.

3.3

Main power input (VDD)

The VDD input is the primary power source of the L9848. This supply is used as the power

source for all of its logic circuitry and other miscellaneous functions. Notice that if the L9848

is interfaced to a processor operating with a lower voltage (e.g. 3.0 VDC), the

microprocessor inputs connected to the L9848 will swing from 0 to 5.0 VDC.

3.4

Discrete inputs (IN5-6)

These inputs allow Output5-6 to be enabled via this external pin without the use of the SPI.

A logic "1" on these inputs enables the corresponding output no matter what the status of

the SPI command register. A logic "0" on these inputs disables the corresponding output if

the SPI command register is not commanding this output on. These pins can be left "open"

if the outputs are controlled only via the SPI (internally pulled down). These inputs are

ideally suited for non-inductive loads that are pulse width modulated (PWMed). This allows

PWM control without the use of the SPI. The TTL level compatible input voltages allow

proper operation with microprocessors that are using 5.0V or 3.0V for their Vdd supply.

3.5

Serial peripheral interface (SPI)

A standard serial peripheral interface, consisting of Serial Clock (SCLK), Data Out (DO),

Data In (DI), and Chip Select (CS) is implemented to allow access to the internal registers of

the L9848. All outputs are controlled via the SPI.The input pins CS, SCLK, and DI have TTL

level compatible input voltages allowing proper operation from microprocessors that are

using 5.0V or 3.0V for their VDD supply. The design of the L9848 allows a "daisy-chaining"

of multiple L9848's to further reduce the need for controller pins.