Functional description

L9848

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3.5.1

Serial data output (DO)

This output pin is in a tri-state condition when CS is a logic "0" (LOW). When CS is a logic

"1" (HIGH), this pin always transmits 8bits of data from the fault register to the digital

controller. After the first 8bits data are transmitted the DO output then sequentially transmits

the digital data that was just received (8 SCLK cycles earlier) on the DI pin. The DO output

continues to transmit the 8 SCLK delayed bit data from the DI input until CS eventually

transitions from a logic "1" to a logic "0". DO data changes state 10 ns or later, after the

falling edge of SCLK. By definition, the MSB (Table 3) is the first bit of the byte transmitted

on DO and the LSB is the last bit of the byte transmitted on DO, once CS transitions from a

logic "0" to a logic "1".

3.5.2

Serial data input (DI)

This input takes data from the digital controller while CS is HIGH. The L9848 accepts an 8bit

data stream to command the outputs ON or OFF. By definition, the MSB (Table 1) is the first

bit of each byte received on DI and the LSB is the last bit of each byte received on DI, once

CS transitions from a logic "0" to a logic "1".

3.5.3

Chip select (CS)

This is the chip select input pin. On the rising edge of CS, the DO pin switches from tri-state

to active-out mode. While CS is high, register data is shifted in and shifted out by the DI and

DO pin, respectively, on each subsequent SCLK. On the falling edge of CS, the DO pin

switches back to tri-state mode and the fault register will be "Cleared" if a valid DI byte was

received.

A valid DI byte is defined as such:

1st A multiple of 8 bits was received

2nd SCLK was low when CS went low

3rd Current SPI cycle started when SCLK was low

The fault data is not cleared unless all of the 3 previous conditions have been met. A SCLK

transition must be seen before CS is interpreted as active. To allow sufficient time to reload

the fault registers, the CS pin must remain low for a minimum of 1µs prior to going high

again, before it starts shifting the fault data bits out on the DO pin. CS has an integrated

glitch filter for spurious pulses of 50ns or shorter (i.e. no fault data and Outputs1-8 enable

status will be altered). For open circuit condition the CS is internally pulled down to GND.

3.5.4

Serial clock (SCLK)

This is the clock signal input for synchronization of serial data transfer. DI data is shifted into

the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK.