AT89C5132-ROTIL datasheet(99/182 Pages) ATMEL

99 / 182 page

4173E–USB–09/07

AT89C5132

MMCON2 (S:E6h) – MMC Control Register 2

Reset Value = 0000 0000b

Table 81. MMSTA Register

MMSTA (S:DEh Read Only) – MMC Control and Status Register

MMCEN

DCR

CCR

DATD1

DATD0

FLOWC

Bit

Number

Bit

Mnemonic Description

MMCEN

MMC Clock Enable Bit

Set to enable the MCLK clocks and activate the MMC controller.

Clear to disable the MMC clocks and freeze the MMC controller.

DCR

Data Controller Reset Bit

Set and clear to reset the data line controller in case of transfer abort.

CCR

Command Controller Reset Bit

Set and clear to reset the command line controller in case of transfer abort.

4 - 3

Reserved

The values read from these Bits are always 0. Do not set these Bits.

2 - 1

DATD1:0

Data Transmission Delay Bits

Used to delay the data transmission after a response from 3 MMC clock periods

(all Bits cleared) to 9 MMC clock periods (all Bits set) by step of 2 MMC clock

periods.

FLOWC

MMC Flow Control Bit

Set to enable the flow control during data transfers.

Clear to disable the flow control during data transfers.

CBUSY

CRC16S

DATFS

CRC7S

RESPFS

CFLCK

Bit

Number

Bit

Mnemonic Description

7 - 6

Reserved

The values read from these Bits are always 0. Do not set these Bits.

CBUSY

Card Busy Flag

Set by hardware when the card sends a busy state on the data line.

Cleared by hardware when the card no more sends a busy state on the data line.

AT89C5132-ROTIL Datasheet(PDF) 99 Page - ATMEL Corporation

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