AT89C5132-ROTIL datasheet(15/182 Pages) ATMEL

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4173E–USB–09/07

AT89C5132

CKCON (S:8Fh) – Clock Control Register

Reset Value = 0000 000Xb

Table 2. PLLNDIV Register

PLLNDIV (S:EEh) – PLL N Divider Register

Reset Value = 0000 0000b

TWIX2

WDX2

SIX2

T1X2

T0X2

Bit Number

Bit

Mnemonic

Description

TWIX2

Two-Wire Clock Control Bit

Set to select the oscillator clock divided by 2 as TWI clock input (X2 independent).

Clear to select the peripheral clock as TWI clock input (X2 dependent).

WDX2

Watchdog Clock Control Bit

Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent).

Clear to select the peripheral clock as watchdog clock input (X2 dependent).

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SIX2

Enhanced UART Clock (Mode 0 and 2) Control Bit

Set to select the oscillator clock divided by 2 as UART clock input (X2 independent).

Clear to select the peripheral clock as UART clock input (X2 dependent)..

Reserved

The value read from this bit is indeterminate. Do not set this bit.

T1X2

Timer 1 Clock Control Bit

Set to select the oscillator clock divided by two as Timer 1 clock input (X2 independent).

Clear to select the peripheral clock as Timer 1 clock input (X2 dependent).

T0X2

Timer 0 Clock Control Bit

Set to select the oscillator clock divided by two as timer 0 clock input (X2 independent).

Clear to select the peripheral clock as timer 0 clock input (X2 dependent).

System Clock Control Bit

Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER = FOSC/2).

Set to select 6 clock periods per machine cycle (X2 mode, F

CPU = FPER = FOSC).

Bit Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is always 0. Do not set this bit.

6-0

N6:0

PLL N Divider

7-bit N divider.

AT89C5132-ROTIL Datasheet(PDF) 15 Page - ATMEL Corporation

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