STV0196 datasheet(7/23 Pages) STMICROELECTRONICS

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II - ADC INTERFACE

II.1 - M_CLK Master Clock Input

This is the highest frequency clock of the chip, at

twice the symbol frequency; all other clocks are

derived from it.

This clock should be output from an external VCO

or VCXO, controlled by CLKREC output.

M_CLK divided by 60 is available to the system

(output D60).

II.2 - I and Q Signal Inputs

Those signals are coded on 6 bits, either in 2’s

complement or as positive values : the choice is

programmable via the Input Configuration register.

The

π/2 ambiguity inherentin QPSK is solved in the

Error Correction part.

A programmable bit in a mode register allows to

multiply by -1 the data on Q input, in order to

accommodate QPSK modulation with another con-

vention of rotation sense ; (this is equivalent to a

permutation of I and Q inputs, or a spectral sym-

metry).

III - NYQUIST ROOT FILTER

The I and Q components are filtered by a digital

Nyquist root filter with the following features :

- Input : separate I and Q streams, two samples per

symbol.

- Excess bandwidth : 0.35 in Mode A.

- The filters may be bypassed ; in this case, the

input flow is connected to the carrier and clock

recovery section.

Input Configuration Register

(the written value of each bit is the reset value)

Internal Address : Hex00

00000100

IV - TIMING RECOVERY

The timing loop comprises an external VCO

or VCXO, running at twice the symbol frequency,

controlled by the output CLKREC ; this signal is a

pulse density modulated output, at the symbol

frequency, and represents the filtered timing

error.

The loop is parametrised by two coefficients : al-

pha_tmg and beta_tmg ; the 12 bit filter output is

converted into a pulse density modulation signal

which should be filtered by an analog low pass filter

before commanding the VCO.

IV.1 - Timing Loop Registers

Time Constant Register

Internal Address : Hex0C

Reset Value : Hex45

Istr

Invert

bit

alpha_tmg (1 to 6)

beta_tmg (0 to 9)

The bit ”Istr” allows to change the polarity of the

output signal, in order to accommodate both pos-

sibilities of external VCO :

Istr

Loop Control

VCO frequency raises when output average

voltage raises

VCO frequency decreases when output

average voltage raises

Timing Frequency Register

Internal Address : Hex0D

Signed number

The value of this register, when the system is

locked, is an image of the frequencyoffset; it should

be as close as possible to 0 in order to have a

symmetric capture range ; reading it allows optimal

trimming of the timing VCO range.

IV.2 - Loop Equations

The external VCO is controlled by the output

CLKREC followed by a low pass filter.

The full analog swing of the output originates a

relative frequency shift of 2

∆f , depending on the

characteristics of the external VCO (typically a

fraction of percent).

The frequency range is therefore f = f0 (1

± ∆f).

Neglecting the analog low pass filter on the pulse

modulated output, this loop may be considered as

a second order loop.

FUNCTIONAL DESCRIPTION (continued)

STV0196B

7/23

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