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H8SX/1663 Datasheet(PDF) 1129 Page - Renesas Technology Corp |
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H8SX/1663 Datasheet(HTML) 1129 Page - Renesas Technology Corp |
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1129 / 1158 page  Section 25 Electrical Characteristics Rev.1.00 Jun. 07, 2006 Page 1077 of 1102 REJ09B0294-0100 25.3.5 Timing of On-Chip Peripheral Modules Table 25.8 Timing of On-Chip Peripheral Modules Conditions: V CC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, V SS = PLLVSS = DrVSS = AVSS = 0 V, Pφ = 8 MHz to 35 MHz, T a = –20°C to +75°C (regular specifications), T a = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions I/O ports Output data delay time t PWD 40 ns Figure 25.39 Input data setup time t PRS 25 ns Input data hold time t PRH 25 ns TPU Timer output delay time t TOCD 40 ns Figure 25.40 Timer input setup time t TICS 25 ns Timer clock input setup time t TCKS 25 ns Figure 25.41 Single-edge setting t TCKWH 1.5 t cyc Timer clock pulse width Both-edge setting t TCKWL 2.5 t cyc PPG Pulse output delay time t POD 40 ns Figure 25.42 Timer output delay time t TMOD 40 ns Figure 25.43 8-bit timer Timer reset input setup time t TMRS 25 ns Figure 25.44 Timer clock input setup time t TMCS 25 ns Figure 25.45 Timer clock pulse width Single-edge setting t TMCWH 1.5 t cyc Both-edge setting t TMCWL 2.5 t cyc WDT Overflow output delay time t WOVD 40 ns Figure 25.46 SCI Asynchronous t Scyc 4 t cyc Figure 25.47 Input clock cycle Clocked synchronous 6 Input clock pulse width t SCKW 0.4 0.6 t Scyc Input clock rise time t SCKr 1.5 t cyc Input clock fall time t SCKf 1.5 t cyc |
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