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H8SX/1663 Datasheet(PDF) 1130 Page - Renesas Technology Corp |
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H8SX/1663 Datasheet(HTML) 1130 Page - Renesas Technology Corp |
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1130 / 1158 page  Section 25 Electrical Characteristics Rev.1.00 Jun. 07, 2006 Page 1078 of 1102 REJ09B0294-0100 Item Symbol Min. Max. Unit Test Conditions SCI Transmit data delay time t TXD 40 ns Figure 25.48 Receive data setup time (clocked synchronous) t RXS 40 ns Receive data hold time (clocked synchronous) t RXH 40 ns A/D converter Trigger input setup time t TRGS 30 ns Figure 25.49 IIC2 SCL input cycle time t SCL 12 t cyc + 600 ns Figure 25.50 SCL input high pulse width t SCLH 3 t cyc + 300 ns SCL input low pulse width t SCLL 5 t cyc + 300 ns SCL, SDA input falling time t Sf 300 ns SCL, SDA input spike pulse removal time t SP 1 t cyc ns SDA input bus free time t BUF 5 t cyc ns Start condition input hold time t STAH 3 t cyc ns Retransmit start condition input setup time t STAS 3 t cyc ns Stop condition input setup time t STOS 1 t cyc + 20 ns Data input setup time t SDAS 0 ns Data input hold time t SDAH 0 ns SCL, SDA capacitive load Cb 400 pF SCL, SDA falling time t Sf 300 ns |
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