H8SXSLASH1663R datasheet(1113/1504 Pages) RENESAS

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Section 22 A/D Converter

Rev. 2.00 Sep. 24, 2008 Page 1081 of 1468

REJ09B0412-0200

22.4

Operation

The A/D converter has two operating modes: single mode and scan mode. First select the clock for

A/D conversion (ADCLK). When changing the operating mode or analog input channel, to

prevent incorrect operation, first clear the ADST bit in ADCSR to 0. The ADST bit can be set to 1

at the same time as the operating mode or analog input channel is changed.

22.4.1

Single Mode

In single mode, A/D conversion is to be performed only once on the analog input of the specified

single channel.

1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by

software, TPU*

1, TMR*2, or an external trigger input.

2. When A/D conversion is completed, the A/D conversion result is transferred to the

corresponding A/D data register of the channel.

3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set

to 1 at this time, an ADI interrupt request is generated.

4. The ADST bit remains at 1 during A/D conversion, and is automatically cleared to 0 when

A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0

during A/D conversion, A/D conversion stops and the A/D converter enters a wait state.

Notes: 1. Only possible in unit 0.

2. As conversion start trigger, units 0 and 1 of TMR, and units 2 and 3 of TMR are

available in unit 0, and unit 1, respectively.

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