H8SXSLASH1663R datasheet(1116/1504 Pages) RENESAS

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Section 22 A/D Converter

Rev. 2.00 Sep. 24, 2008 Page 1084 of 1468

REJ09B0412-0200

(2)

One-Cycle Scan Mode (only enabled in unit 1)

1. Set the ADSTCLR bit in ADCR to 1.

2. When the ADST bit in ADCSR is set to 1 by software, TMR (units 2 and 3), or an external

trigger input, A/D conversion starts on the first channel in the specified channel group.

Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10)

can be selected. For unit 1, A/D conversion starts on AN4 when CH3 and CH2

= B’01.

3. When A/D conversion for each channel is completed, the A/D conversion result is sequentially

transferred to the corresponding ADDR of each channel.

4. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1.

If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated.

5. The ADST bit is automatically cleared when A/D conversion is completed for all of the

channels that have been selected. A/D conversion stops and the A/D converter enters a wait

state.

A/D conversion result 1

A/D conversion result 2

A/D conversion result 3

A/D conversion time

A/D conversion one-cycle execution

ADST

ADF

ADDRE

ADDRF

ADDRG

ADDRH

Channel 4 (AN4)

operation state

Channel 5 (AN5)

operation state

Channel 6 (AN6)

operation state

Channel 7 (AN7)

operation state

Set *

Clear*

Waiting for conversion

Transfer

Waiting for conversion

A/D conversion 1

A/D conversion 2

A/D conversion 3

Note:

↓ indicates the timing of instruction execution by software.

Figure 22.5 Example of A/D Conversion

(One-Cycle Scan Mode, Three Channels (AN4 to AN6) Selected)

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