H8SXSLASH1663R datasheet(1115/1504 Pages) RENESAS

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Section 22 A/D Converter

Rev. 2.00 Sep. 24, 2008 Page 1083 of 1468

REJ09B0412-0200

When consecutive A/D conversion is performed on eight channels*

1, A/D conversion starts on

AN0 when CH3 = B'0.

2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially

transferred to the corresponding ADDR of each channel.

3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1.

If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of

the first channel in the group starts again.

4. The ADST bit is not cleared automatically, and steps 2 to 3 are repeated as long as the ADST

bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D

converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from

the first channel in the group.

Notes: 1. Consecutive A/D conversion on eight channels is only possible in unit 0.

2. As conversion start trigger, units 0 and 1 of TMR, and units 2 and 3 of TMR are

available in unit 0, and unit 1, respectively.

ADST

ADF

ADDRA

ADDRB

ADDRC

ADDRD

Set*1

Clear*1

Waiting for conversion

Channel 0 (AN0)

operation state

Channel 1 (AN1)

operation state

Channel 2 (AN2)

operation state

Channel 3 (AN3)

operation state

Waiting for

conversion

A/D

conver-

sion 1

A/D conversion result 3

Waiting for conversion

Waiting for

conversion

Waiting for conversion

A/D conversion result 2

A/D conversion result 4

A/D

conver-

sion 5

A/D

conver-

sion 4

A/D conversion time

Waiting for conversion

A/D

conver-

sion 3

Waiting for conversion

A/D

conver-

sion 2

A/D conversion result 1

Transfer

A/D conversion consecutive execution

Notes: 1.

↓ indicates the timing of instruction execution by software.

Data being converted is ignored.

Figure 22.4 Example of A/D Conversion

(Continuous Scan Mode, Three Channels (AN0 to AN2) Selected)

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